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        <dc:title>Arm CoreSightArchitecture Specification v3.0</dc:title>
        <dc:creator opf:file-as="ARM" opf:role="aut">ARM</dc:creator>
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        <dc:date>2022-02-21T13:01:32+00:00</dc:date>
        <dc:description>ARM CoreSight Architecture Specification. Defines the architecture for debug and trace of Cortex processors, DSPs and graphic processors. The ROM table aids topology detection. Includes ETB, ETM, CTI, CTM, Replicators, Formatter, ATB, SWDO, SWJ-AP, SWJ-DP, Serial Wire Output SWO. PDF document</dc:description>
        <dc:language>en</dc:language>
        <dc:subject>ARM CoreSight Architecture Specification. Defines the architecture for debug and trace of Cortex processors</dc:subject>
        <dc:subject>DSPs and graphic processors. The ROM table aids topology detection. Includes ETB</dc:subject>
        <dc:subject>ETM</dc:subject>
        <dc:subject>CTI</dc:subject>
        <dc:subject>CTM</dc:subject>
        <dc:subject>Replicators</dc:subject>
        <dc:subject>Formatter</dc:subject>
        <dc:subject>ATB</dc:subject>
        <dc:subject>SWDO</dc:subject>
        <dc:subject>SWJ-AP</dc:subject>
        <dc:subject>SWJ-DP</dc:subject>
        <dc:subject>Serial Wire Output SWO. PDF document</dc:subject>
        <dc:subject>CoreSight</dc:subject>
        <dc:subject>CoreSight Architecture</dc:subject>
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